Makers of today's electronic equipment consistently pressure IC manufacturers to: (1) reduce the sizes of ICs, and (2) maintain or increase the number and complexity of the functions the ICs perform. Therefore, IC designers continue to explore and develop new techniques for reducing the areas of IC dies without reducing the ICs' capabilities.
FIG. 1 is a block diagram of an IC 10, which includes an array 12 of memory cells and redundancy circuitry for replacing defective ones of the cells. The array 12 includes a matrix array 14 of matrix memory cells that store data and that are arranged in rows and columns. An address generator 18 receives an external address on the ADDRESS bus and generates therefrom an internal row address on a bus 20. This internal address identifies a respective row of matrix cells in the array 14. A matrix circuit 21 includes matrix row decoders 22.sub.0 -22.sub.n --one for each row in the matrix array 14--for firing the respective matrix rows.
In operation of the IC 10, the decoders 22.sub.0 -22.sub.n receive a conventional address PRECHARGE signal before the generator 18 generates the row address. Next, the row decoders 22.sub.0 -22.sub.n receive and decode the row address on the bus 20. Then, the row decoder 22 corresponding to the addressed row fires the word line WL of the addressed row. For example, if the address generator 18 addresses row 0 in the matrix array 14, then the row 0 decoder 22.sub.0 fires the word line WL0 via a firing terminal 25.sub.0.
Unfortunately, one or more matrix cells in a row of the matrix array 14 may be defective and thus unable to reliably store data. For example, the respective word line WL or a part of the defective matrix cell or cells may be short-circuited to other nodes in the IC 10.
To prevent a defective matrix cell from rendering the entire IC 10 unusable, the array 12 includes an array 23 of redundant memory cells, and the IC 10 includes a redundant circuit 24 for mapping a redundant cell to the address of a defective matrix cell. In one embodiment, the redundant cells are arranged in rows and columns, and the circuit 24 maps a redundant row to the address of a matrix row containing one or more defective matrix cells. The circuit 24 includes a programmable portion 26 and redundant row decoders 28.sub.0 -28.sub.x --one decoder for each row in the redundant array 23--for firing the respective redundant rows. The programmable portion 26 includes a programmable redundancy address circuit 30 and a programmable redundancy control circuit 32. Often, the circuits 30 and 32 contain laser-programmable fuses that are laid out side by side in a lower layer of the IC 10.
If one finds a defective row in the matrix array 14, then he programs the circuit 24 to map a redundant row in the array 23 to the address of the defective matrix row. For example, suppose that matrix row 1 is defective and one wishes to replace it with the redundant row 0. To do this, he programs the redundancy address circuit 30 to address the redundant row 0--and thus to activate the redundant row decoder 28.sub.0 --whenever the address generator 18 generates the address of the matrix row 1. He also programs the redundancy control circuit 32 to enable the redundant row decoder .sup.28 0. Therefore, in response to the redundant-row-0 address from the circuit 30 and an enabling control signal from the circuit 32, the redundant row decoder 28.sub.0 fires the redundant word line RWL0 via a firing terminal 29.sub.0.
A problem with the matrix circuit 21, however, is that it continues to fire the word line WL of a defective matrix row even after one has programmed the redundant circuit 24 to replace the defective row with a redundant row. This firing may cause a malfunction that is not fixed by the mapping of the redundant row to the address of the defective row. For example, if the word line WL of the defective row is shorted to another word line or to a cell plate, then firing WL may cause data errors or other malfunctions.
FIG. 2 is a block diagram of an IC 40, which is similar to the IC 10 of FIG. 1 except that the matrix circuit 21 does not fire a defective matrix row. The matrix circuit 21 includes a programmable matrix control circuit 42. If one finds a defective matrix row in the array 14, then in addition to programming the redundant circuit 24 as discussed above in conjunction with FIG. 1, he programs the circuit 42 to disable the corresponding row decoder 22 from firing the word line WL of the defective row. For example, if the matrix row 0 is defective, then one programs the control circuit 42 to disable the row decoder 22.sub.0. Thus, even if the address generator 18 generates the address of the matrix row 0, the disabled row decoder 22.sub.0 does not fire the word line WL0.
Often, the matrix control circuit 42 includes laser fuses that are disposed in the same layer of the IC 40 as the fuses of the redundant circuit 24. Therefore, the circuit 42 tends to increase the die area, and thus the overall size, of the IC 40.
FIG. 3 is a cutaway cross-sectional view of a semiconductor structure 50, which includes a stacked fuse 51. The structure 50 includes an upper fuse element 52 disposed on an insulator layer 54, and includes a lower fuse element 56 disposed beneath the insulator layer 54 and in alignment with the upper fuse element 52. The fuse elements 52 and 56 are electrically connected in parallel by conductive vias 58 and 59 to form the stacked fuse 51. Compared to a single fuse element, the stacked fuse 51 has approximately the same width, and thus occupies approximately the same die area, but has approximately twice the current-carrying capacity. During programming of the stacked fuse 51, one uses a laser beam to cut both fuse elements 52 and 56.
Unfortunately, including stacked fuses in the IC 40 would not reduce the number of fuses in the circuits 30, 32, and 42, and thus would not reduce the die area of the IC 40. In fact, including stacked fuses in the IC 40 would increase the manufacturing complexity of and could add a conductive layer to the IC 40.